A reconfiguration solution for CMOS frequency synthesizer in cognitive radio devices

Abstract

This article proposes a reconfiguration solution for CMOS frequency synthesizer with a hybrid architecture which is a combination of a DDS and a PLL. The DDS is implemented in FPGA platform functioning a referrence frequency for the PLL. The PLL is designed using CMOS technology, and is reconfigurable to accelerate tuning speed. Instead of employing a hardwarebased lock detector, a software algorithm is used to determine the switching time and to optimize the tuning speed, consumption energy or average power. This PLL is used in cognitive radio for spectrum sensing function.